CHAPTER 1: INTRODUCTION Non-Planar MOSFET’S were first discovered in 1994 but at that time it was not economically or technological practical to shift from planar to non-planar as it was quite difficult to change and till then there were no difficulties in shrinking traditional MOSFET’S. But in 2005 the shrinking and manufacturing became difficult due to Quantum effects which were increasing exponentially with decrease in size. For further continuation of Moore’s Law we shifted towards the most favorable option Non-Planar MOSFET’s which provide better control of the channel by incorporating more number of gates most famous being FINFET due to ease in manufacturing and fabrication. Today FINFET’s have reached their limit too as the decrease in transistor size was tradeoff for increase in resistive and capacitive parasites. In this study we discuss the structures of Non-Planar MOSFET’S and probable successors of FINFET’S4. 1.1 Need For Study The study’s aim is to trace the key developments and changes in technologies and structures of traditional MOSFET’S.
It compiles the data from various researches all over the globe in last three decades and provides a brief review of the same. It also provides statistical data and performance graphs for the comparison with planar MOSFET’s. It covers both pros and cons of new technologies both on commercial and technological basis. 1.2 Non-Planar FETs Non-Planar FET’s are quasi-planar devices. In them the silicon body has been rotated on its edge into a vertical orientation so only source and drain regions are placed horizontally about the body, as in a conventional planar FET. NON PLANAR MOSFET comprises of a conducting channel (usually undoped), surrounded by gate electrodes on either side.
This ensures that no part of the channel is far away from a gate electrode. A multigate device employing independent gate electrodes is sometimes called a Multiple Independent Gate Field Effect Transistor (MIGFET)1. Fig 1 : Non-Planar FET’s general structure1 Traditional planar FET or MOSFET Dual gate planar FET or DGFET Tri gate non-planar FET FINFET Quadruple gate or Gate all around FET OR GAAFET Nano wire FET or NWFET CHAPTER 2: NON-PLANAR VS PLANAR FET’s Information on the technologies used are given below: Table 1: Technology characteristics 1016038100 Minimum Gate Supply Fin height / width / gate length Pitch Voltage pitch N10 (low Vt) 20nm 64nm 0.7V 30nm/6.7nm/36nm N28 (low Vt) 30nm 130nm 0.9V – FinFET devices are able to meet a spec on gm at much lower inversion levels than their planar equivalents, especially for short gate devices (Fig. 1).
This characteristic should be exploited when designing with FinFETs as it is at low inversion levels that the highest power efficiencies and intrinsic gain values can be achieved (Fig. 2 and 3). However, the advantage N10 (FinFET) has over N28 (planar) for short gate devices becomes less significant as gate length increases1. center14605 Graph 1 Normalized transconductance (gm) for |VDS| = VDD. Left side of plot represents gm of PMOS devices (VGS ; 0); right side concerns NMOS devices (VGS ; 0).
Higher gm values at lower overdrives can be obtained in N10, especially in the case of PMOS devices1. FinFETs offer much higher intrinsic gains (gm/gds) than transistors in N28, so long as low inversion biases are used. This is due to the better electrostatic control of the channel FinFETs have over planar devices, especially for short gate devices. This is not the case in N28 where intrinsic gain values rapidly drop when gate lengths scale down. From the figures discussed above, it is apparent that transistors have (at low frequencies) more desirable characteristics at low inversion levels.
However, for a given current or gm value, the width of a transistor increases as the overdrive applied is reduced, which increases the surface it occupies and its parasitic capacitance. There is therefore a trade-off between a transistor’s biasing level and its dimensions. One of the effects of high parasitic capacitance is illustrated in graph4 which plots the cutoff frequency fT ? gm/2?Cgg as a function of current density. In this respect, FinFETs perform less well than the planar devices we compare them to. Although their gm is higher for a given current, the ratio of that gm to the gate capacitance (Cgg) of the device is lower in N10 because of extrinsic resistive and capacitive parasitics4. 108267519050 Graph 2 Power efficiency of NMOS and PMOS devices as a function of current density, |VDS| = VDD.
Curves show N10 FinFET has higher gm/I ratios than N28 planar, but this efficiency gap reduces as gate length increases4. 140296015240 Graph 3 Intrinsic gain of NMOS and PMOS devices as a function of current density, |VDS| = VDD. At low current densities, higher intrinsic gains are achieved in N10. Even short gate devices can attain over 30dB of gain, which is not the case in N284. 146639216510 Graph 4 Cutoff frequency (calculated as fT ? gm/2?Cgg) of NMOS and PMOS devices as a function of current density, |VDS| = VDD. N28 planar devices are able to reach higher cutoff frequencies because they suffer from less parasitics, both resistive and capacitive4.
2.1 Dual Gate FET Traditional downscaling device technologies have been serving the microelectronic industry over the last three decades. Scaling with new materials & new device structures are now continually improving the performance of device technologies. DG-MOSFETs seem to be a very promising candidate owing to its excellent SCEs suppression, higher drive current and transconductance, lower leakage current, better DIBL and better scaling capability compared to the bulk MOSFETs19. There are six different structures for DG- MOSFET :- Fig 2(a) Gate Stack Double Gate19 Fig 2 (b) GS-DG-Single Halo19 847710-152903 Fig 2 (c) GS-DG-Double Halo19 843294113842 Fig 2(d) GS-DG Tri-material19 8149263337 Fig 2(e) GS-DG Tri-material Single Halo 19 Fig 2 (f) GS-DG Tri-material Double Halo19 In the structures, the channel length (L) and Source/Drain length (LS/LD) is kept as 40nm. The silicon thickness (TSi) as 10nm and a uniform density ND as 1020 cm-3 is taken.
The channel is doped with impurity concentration of NA=1016 cm-3. In each case the effective oxide thickness is 1.1625nm. The thickness of SiO2 and equivalent HfO2 are 1nm, 0.1625nm respectively. To get equivalent thickness of the high -k as 0.1625nm, the physical thickness is 1nm. The work function for the gate electrode is assumed as 4.8ev for single material DG-MOSFETs. The channel engineering SH and DH was implemented in GS-DG models in a ratio of 1:4 and 1:2:1 respectively with NA= 1018 cm-3 as shown in Figure 1(b) &(c).
The control gate M1 (toward the source side) and screening gates M2 and M3 (toward the drain side) are the gate electrodes with lengths LM1, LM2 and LM3 (LM1: LM2:LM3 = 1:2:1) and with metal work functions q?M1, q?M2 and q?M3 (4.8ev, 4.6ev &4.4ev)20. CHAPTER 3: MANUFACTURING AND FABRICATION SOI wafers are thermally oxidized to pro-duce 50-nm silicon films with a 50 nm hard-mask oxide. Phosphorus implants are used to achieve n-type channel doping in the range of 13 cm3 to 18 cm3. A double-resist process is used to define narrow gates and large-area patterns simultaneously.
250-nm optical G-line resist is patterned first and hard baked at 170 C; 200-nm SAL-601 is subsequently coated and patterned using e-beam exposure providing critical gate dimensions down to 30 nm. The two resist patterns are then transferred to the SOI with a single re-active ion etch (RIE). After the silicon fins are etched, 2.5-nm sacrificial oxide is grown and removed to improve the gate side-wall surface prior to gate oxidation without seriously undercut-ting the buried oxide. The gate stack includes a 50-m oxide hard mask on top of 240-nm in-situ boron-doped Si0.5Ge0.5 on 1.8-nm SiO gate oxide.
The SiGe gate composition is chosen to provide the desired threshold voltage. The gate-to-drain misalignment tolerance is 100 nm, but tighter tolerances can be achieved with improved e-beam stepping software. The triangular hard-mask shape and the trapezoidal gates are a result of using CHF3 during part of the Si RIE. After double-layer spacers of 37.5-nm nitride on 10-nm oxide are formed, arsenic and phosphorus ions are implanted to form the source and drain. A 600C anneal is used to re crystallize any portion of the silicon fin amorphized by the heavy As implant.
This is followed by a short 900C activation anneal and a 450C forming gas anneal. 21 Fig. 3 Fabication of MOSFET 3.1 Electron Beam Lithography Electron-beam lithography (often abbreviated as e-beam lithography) is the practice of scanning a focused beam of electrons to draw custom shapes on a surface covered with an electron-sensitive film called a resist (“exposing”). The electron beam changes the solubility of the resist, enabling selective removal of either the exposed or non-exposed regions of the resist by immersing it in a solvent (“developing”). The purpose, as with photolithography, is to create very small structures in the resist that can subsequently be transferred to the substrate material, often by etching.
The primary advantage of electron-beam lithography is that it can draw custom patterns (direct-write) with sub-10 nm resolution. This form of maskless lithography has high resolution and low throughput, limiting its usage to photomask fabrication, low-volume production of semiconductor devices, and research and development. Electron-beam lithography systems used in commercial applications are dedicated e-beam writing systems that are very expensive (> US$1M). For research applications, it is very common to convert an electron microscope into an electron beam lithography system using a relatively low-cost accessory.
Such converted systems have produced linewidths of ~20 nm since at least 1990, while current dedicated systems have produced linewidths on the order of 10 nm or smaller. 10 Fig. 4: (a) Writing strategy in bell laboratories Electron Beam Exposure “EBES” 10 (b) Schematic view of EBES 10 Fig. 5 Schematic view of patterning metal by lift-off. The undesired metal is removed by rapidly dissolving exposed and developed resist 10 6.2 Resist Layer Resist layer should be sensitive to imaging radiation (in our case an electron beam) and resistant to the subsequent etching of underlying circuit material or to whatever other process is used to transfer the pattern from the resist to the circuit material. Such processes include lift-off and selective plating, and even ion implantation in which the resist pattern acts as a barrier to the ion beam.
The main requirements of a resist film are that: It is sufficiently sensitive to the electron beam. It is sufficiently robust to survive the subsequent pattern transfer process. It is sufficiently thick to be effectively free from defects. It affords adequate resolution of the pattern. The resist can be stripped after the pattern has been transferred.
21 CHAPTER 4: FINFET’S In 1989, Hisamato et al. fabricated a double-gate SOI structure which they called a fully-depleted lean channel transistor (DELTA). This was the first reported fabrication of a FinFET-like structure. FinFETs have attracted increasing attention over the past decade because of the degrading short-channel behavior of planar MOSFETs.
While the planar MOSFET channel is horizontal, the FinFET channel (also known as the fin) is vertical. Hence, the height of the channel (FIN) determines the width of the FinFET. This leads to a special property of FinFETs known as width quantization. This property says that the FinFET width must be a multiple of FIN, that is, widths can be increased by using multiple fins. Thus, arbitrary FinFET widths are not possible.
Although smaller fin heights offer more flexibility, they lead to multiple fins, which in turn leads to more silicon area. On the other hand, taller fins lead to less silicon footprint, but may also result in structural instability. Typically, the fin height is determined by the process engineers and is kept below four times the f in thickness. Although FinFETs implemented on SOI wafers are very popular, FinFETs have also been implemented on con-ventional bulk wafers extensively.
Figure 3 shows FinFETs implemented on bulk and SOI wafers. Unlike bulk FinFETs, where all fins share a common Si substrate (also known as the bulk), fins in SOI FinFETs are physically isolated. Some companies prefer the bulk technology because it is easier to migrate to bulk FinFETs from conventional bulk MOSFETs. However, FinFETs on both types of wafers are quite comparable in terms of cost, performance, and yield, and it is premature to pick a winner. Fig. 6 FINFET device schematic4 Trigate FETs, referred to interchangeably as FinFETs, are a variant of FinFETs, with a third gate on top of the fin.
Intel introduced Trigate FETs at the 22 nm node in the Ivy-Bridge processor in 2012. The thickness of the dielectric on top of the fin is reduced in Trigate FETs in order to create the third gate. Due to the presence of the third gate, the thickness of the fin also adds to the channel width. Hence, Trigate FETs enjoy a slight width advantage over FinFETs. Trigate FETs also have less gate-source capacitance compared to FinFETs due to additional current conduction at the top surface, but this advantage is diminished by increased parasitic resistance4. 4.1 Fabrication A thin vertical structure is raised over the surface of the silicon surface.
On the either side of the thin fin an oxide layer is deposited. The oxide layer provides isolation between gate and substrate. Poly silicon gate is rolled over vertically raised fin in such a way that the gate rests on oxide on the either side of the high raised fin. Two parts of the fin extends on the either side of the gate. These are called drain and source, same as in case of planar MOSTEs. The fin passes through gate which looks like tunnel.
The desired performance can be achieved by varying fin thickness and gate width and types of materials largely. Such a gate structure provides better control over current flowing in the fin. Simulation is done for a proposed FinFET.21 Fig. 7 (a) Physical structure of FinFET Fig.7 (b) Side view Fig 7 (c) Top view Fig. 8 Fabrication Process 4.2 Functioning of FINFETs The drain to source voltage causes current flow in the fin if there is a suitable gate voltage across source and gate. The gate voltage draws free charges in the fin from substrate and bulk.
Due to free charge carriers presence in the channel a source to drain current starts flowing. The threshold voltage is much lower compared to MOSFETs. Normally, in planar MOSFET, the function of gate biasing is related to drain current control process. Actually drain current will depend upon the channel nature.
The channel formation is much dependent upon gate biasing. One side of the gate is parallel to the channel separated by a thin silicon oxide which insulates channel from gate. Though, the control on drain current by gate voltage is quite efficient and sufficient for an operation of MOSFET. As the MOSFET technology is reduced below 22 nm, the MOSFET needs better control on the drain current.
The alternative technique, to have efficient control on drain current, relates to FinFET concept. Here, the channel is surrounded by gate on three sides.4 Graph 5 Drain current vs gate voltage Graph 6 Drain current vs source voltage 4.3 Nanolithography The semiconductor industry has been stuck with the 193nm lithography even for the most advanced 28nm/22nm nodes now. There are several candidate nanolithography technologies for 14nm, 11nm, 7nm and 1× nm for extreme scaling: multiple patterning lithography (MPL), extreme ultraviolet lithography (EUVL), electron beam lithography (EBL), and so on. MPL is a natural extension of double patterning lithography (DPL).
At the concept level, it just repeats the single patterning lithography by using two or more mask/patterning processes individually to form coarser patterns and then combine them to form finer pitches. Several DPL/MPL technologies have been developed, with different design/process requirements. There are two main types of technologies: litho-etch-litho-etch (LELE) and self-aligned double patterning (SADP). Both of them can be extended for multiple patterning.
LELE splits the original design into two masks when the distance between two patterns is less than minimum colorable distance; otherwise, coloring conflict occurs. The different masks are represented by different colors. Coloring conflict can be resolved by inserting stitches to split a pattern into two touching parts. However, stitches lead to yield loss due to overlay error. SADP uses sidewall spacer to help achieve finer pitch and resolution.
It first generates the core mask. Then unit-width sidewall spacer will be deposited on all sides of the core mask. The second mask (trim mask) will trim out wanted patterns. SADP needs more processing steps than LELE, but has better overlay control.
However, SADP does not allow any stitch insertion and neither it allows variable width/spacing in general, thus it puts more layout constraints. All types of DPL/MPL require layout decomposition. To make design is DPL-compliant, early DPL aware physical design such as DPL-aware routing is necessary.6 EUVL wavelength is 13.5nm, which is good for lithographic resolution. However, EUVL still has tremendous technical barriers such as lack of power sources and defect-free masks. EUVL has several unique challenges compared with conventional lithography. First, flare is inversely proportional to the square of the wavelength, thus EUVL suffers much higher flare effect caused by surface roughness and light scattering.
Flare will degrade aerial image contrast and wafer pattern uniformity. The second major issue of EUVL is the 3D mask effect such as mask shadowing and multi-layer reflection because EUVL system is not governed by projection masks (as in conventional optical lithography), but reflective mirroring masks. Other key issues with EUVL include line edge roughness (LER) and mask defects.8 EBL is a maskless lithography technology which directly writes layout patterns into the silicon wafer, using charged e-beams. The primary advantage is that the electron wavelength is in the order of 0.001nm which easily beats the diffraction limit of light of other lithography.
However, EBL throughput is the biggest bottleneck as the write time is mainly determined by the number of shots.8 4.4 Implementations A. Intel Broadwell 14 Intel’s 14–nm Broadwell chip was shipped in the second quarter of 2014, initially into laptop computers. It is a dual-core microprocessor with a claimed 1.9 billion transistors and a die size of 82 mm2, which is about 50% shrink compared to the 157 mm2 die used for their 22-nm process generation microprocessor. A replacement metal gate (RMG) process flow, first introduced at the 45-nm process generation, was modified for the 32-nm and 22-nm process generations, and continues with further modifications to be used for transistor fabrication in the 14 nm process. The transistor structure that was completely changed from the traditional planar configuration to a tri-gate fin-based 3D configuration for the 22-nm has been further refined for the 14-nm generation, to provide 2nd-generation tri-gate transistors for achieving increased density, lower capacitance and lower power.
The fins have a more vertical profile than the 22-nm version, still with rounded tops. As in all Intel’s RMG The minimum fin pitch has shrunk to ~42 nm from ~60 nm, and the minimum gate lengths seen are ~22 nm. Contacted gate pitch (CGP) is ~70 nm. Fin widths vary considerably, from ~7– 11 nm in Fig. 1, and the NMOS fins are wider than PMOS fins.
The functional fin height was ~37 – 40 nm, giving a gate wrap-around of ~85 nm; this is the effective gate width for a single-fin transistor. One of the innovations announced by Intel in their IEDM 2014 paper 2 was the use of solid-state doping to form a diffused sub-fin punch-stopper, doping the fin below the gate area.The gate stack in the 14-nm process appears to be the same as in the 22-nm, using TiN work-function (WF) material for PMOS, and TiAlC for NMOS; with the exception that the PMOS gate fill is predominantly TiAlN, while NMOS gates have tungsten fill – see Fig. 2. While the gate materials are squeezed into an ever smaller volume, the high-k and oxide gate dielectrics are both still ~1.0 – 1.2 nm thick.Again the top of the gate stack was back-etched and filled with dielectric, to allow the use of self- aligned contacts.In the source/drains, the PMOS epi-SiGe takes the planes, whereas the NMOS epi only shows growth at the base. In both cases the contact wraps around the epi without excessive etching of the epi . Titanium was again used as the contact interface metal.
B. Intel Atom “Cherry trail” SoC 14 As in earlier generations, Intel also launched a SoC version of the process, with low-power logic and high-voltage transistors in addition to the high-speed logic devices seen in the CPU process, and also precision passive components. The SoC process uses a dual-gate oxide flow to form the two groups of transistors; the high-speed and low-power logic devices, and the high-voltage transistors. The high-voltage transistors use a thick gate oxide dielectric and larger gate lengths and pitch to give greater voltage tolerance, similar to the prior RMG generations. The gate stack is the same as the 14- nm logic process, but as stated the interfacial oxide is considerably thicker at ~4 nm.
Gate lengths are of course longer at ~150 nm. C. Qualcomm MDM9235(TSMC 20 nm HPM HKMG Process) 18 Almost simultaneously to the Intel Broadwell, Qualcomm were shipping their MDM9235 modem, fabricated by TSMC in their 20-nm planar HKMG process. This was TSMC’s second-generation RMG HKMG process, showing significant changes from their 28-nm version. Minimum contacted gate pitch was reduced to 90 nm, with minimum observed gate length of ~32 nm.
The high-k and oxide gate dielectrics are both ~1.3 nm thick.Both the transistor gate structure and the deposition sequence of the metal gates had been modified compared to the 28-nm process. In the new flow, the PMOS gate metal was deposited first and then NMOS gate metal was deposited, the reverse of the 28-nm HKMG process. In addition, the high-k dielectric was deposited after the poly gate removal, as opposed to deposition prior to the sacrificial poly formation. D. Samsung Exynos 7420 (14 nm Gate-Last HKMG FinFET Process) 22 Samsung launched their 14-nm LPE FinFET process in the applications processor in the Samsung Galaxy S6 mobile phone in early 2015.The minimum CGP was scaled to 78 nm, with the smallest observed gate length ~28 nm, and a fin pitch of ~48 nm. High-k and oxide dielectric thicknesses were both ~1.3 nm.
The fins have vertical sidewalls similar to Intel’s. The functional fin height was ~38 nm, and fin width ~7 nm; giving a gate wrap-around of ~85 nm, the gate width for a single-fin transistor. As in the other RMG HKMG parts, the PMOS WF layer was formed first, removed, and then the NMOS TiAlC layer was deposited. In the minimum-length gates the fill is TiN, but this appears to be the liner for tungsten fill seen in in longer gates – there is insufficient room for the W to deposit in the short gates.
The epi in both cases has merged, unlike Intel, and there is significant etching of the epi during the contact etch. The growth conditions of the NMOS epi have also produced multiple dislocations in the crystalline structure. In common with Intel, the source/drains are Ti-silicided. E. Apple APL1022 Application Processor (TSMC 16-nm FinFET)23 TSMC’s first finFET process appeared with some fanfare in the A9 processor in the fall of 2015 in the Apple iPhone 6 and 6 Plus mobile phones.
TSMC gave two papers detailing their 16-nm processes 4, 5, neither of which gave any clue of what the transistors actually looked like. The PMOS fin looks slightly slimmer; but the difference is ~6.8 nm vs ~6.2 nm at half-height – or about two atoms! Contacted gate pitch was the same as the 20-nm planar process at 90 nm, and minimum observed gate length was similar at ~30 nm. Fin pitch was ~48 nm. The functional gate height was ~39 nm, and gate wrap-around (gate width) is similar to the other finFETS that we have discussed, at ~85 nm. The PMOS and NMOS gates; similar to Intel, the top of the gates has been back-etched and capped with silicon nitride, even though it does not appear the contacts are self-aligned. Again, the PMOS WF layer (TiN) was formed before the NMOS, and the NMOS WF layer (TiAlCOF) in the PMOS stack allows less room for the tungsten gate fill.
High-k and oxide dielectric thicknesses were both ~1.3 nm. The PMOS displays the typical diamond shape, with ~55% Ge in the SiGe; but we can see that in the NMOS while there is epi growth, the contact etch has removed much of it (we could almost describe it as a recessed contact). TSMC followed the trend and used titanium silicide on the source/drains. As a foundry SoC process, a dual-gate oxide flow is used for core and I/O devices. Similar to Intel, the gate stacks and source/drain structures appear to be the same as the logic transistors, with a thicker gate oxide (PMOS ~4 nm, NMOS ~ 3.5 nm) and longer gates. CHAPTER 5: TECHNOLOGY AND TRANSISTOR BEYOND 7nm A.
NWFET OR Nano wire FET Fig. 9 Nano wire FET15 A combination of a NW channel with GAA configuration has been recognized as an effective approach to alleviate the short-channel effects (SCEs) occurring to nanometer-scale transistors. On the other hand, Junction Less transistors have also attracted many interests nowadays since it is free from the formidable junction fabrication steps15. 5.1 Fabrication First n+ poly-Si SID studs were built on a Si substrate that is encapsulated with a nitride/oxide stack. Note that the studs were expanded with a sidewall spacer to shorten the channel length (L). Following the deposition of an in situ phosphorous-doped poly-Si channel layer, a dummy oxide structure with sidewall spacer layers of nitride is subsequently formed.
The dummy oxide is selectively removed to leave the nitride hardmask for subsequent etching of the NW channel. The NW became suspended once the top nitride and underlying nitride layers were stripped off. Next, a 10 nm-thick Si02 layer and a 150 nm-thick n+ poly-Si layer were deposited as the gate oxide and electrode, respectively, to complete the formation of the GAA structure1. Fig. 10 Schematic processes flow for the transistor1 B.
III-V NANO Electronics Recently, there has been much research interest to extend the benefits of transistor scaling to the iii-V Nano electronics and investigate the possibility of incorporating high mobility compound semiconductor as the device channel material in comparison with the conventional Si NMOS devices, these n-channel iii-V transistors exhibit significantly superior intrinsic speed (CV/I) for a given physical gate length. The iii-V devices also show significantly improved energy-delay product over their Si counterparts due to the lower supply voltage (Vcc = 0.5 V) of operation and higher effective mobility. However, for low-power, high-speed ULSI digital logic applications, the iii-V transistors additionally need to have high Ion/Ioff ratio, to minimize the stand-by power consumption. Despite demonstrating superior intrinsic gate delay, exhibit a limited Ion/Ioff range, due to the Schottky metal gate leakage. These results highlight the urgent need for a high quality high-K dielectric/metal gate technology for the iii-V Nano electronic devices.
It is likely that the use of a gate dielectric between the metal gate and the iii-V device layers will eliminate such Schottky gate leakage and improve the Ion /loff ratio, while still maintaining device performance. The challenges of incorporating iii-V Nano electronics for ULSl digital logic applications include continued aggressive scaling of the transistor physical dimensions, demonstration of a high quality high-K dielectric interface with iii-V semiconductor, the improvement of the Ion/loff range of the iii-V devices, demonstration of high performance p-channel iii-V devices for complementary logic applications, and, finally, wafer scale integration of these extremely large lattice mismatched iii-V materials system onto the Si platform6. Fig. 11 Three dimensional MOSFET fabrication 6 C.
Absorbance Modulation Optical Lithography (AMOL) (Patterning beyond the diffraction limit) The size of the smallest features that can be fabricated by means of conventional optical lithography in the semi-conductor industry is fast approaching its limits due to far-field diffraction. Conventionally this is limited to approximately to half the wavelength of the illuminating light. However, Absorbance Modulation Optical Lithography (AMOL), an alternative optical lithographic technique, has been shown to effectively pattern Nano scale features beyond the diffraction limit. The conventional AMOL process employs a thin layer of a two-state-photo-switchable photochromic material, as an absorbance modulation layer which is exposed simultaneously to wavelength ?2 with a node at the center (experimentally realized by using a standing wave) and uniform illumination at another wavelength ?1. Absorption at the first wavelength ?1 (UV – 325 nm) converts the photochromic layer into a transparent form, while absorption at the 2nd wavelength, ?2 (visible – 647 nm) renders the photochromic layer opaque.
It is then possible to squeeze the transmission of ?1 through the photochromic layer by the competing action of the two states of the photochromic material under the influence of the two wavelengths, leading to the formation of a Nano-scale optical probe on the other side. An underlying recording medium such as photoresist layer can capture the ?1 light that transmits through the aperture and thereby record a sub diffraction pattern in the photoresist. One important feature of AMOL is that the size of the pattern in the resist can be scaled according to the ratio of the intensities of ?2 and ?1 instead of simply the absolute intensity of either beams 18. Fig.
12: (a) Photo-switch-ability of the photochromic molecule used in AMOL (b) Sample stack with photoresist as a recording medium below the layer of photochromic molecules and simultaneous exposure at two wavelengths. The sample stack is free from the presence of any barrier layer. 18 CHAPTER 6: CONCLUSION AND FUTURE SCOPE At the end we conclude that advantages of FINFET outweighs its disadvantages till 7nm for beyond that it suffers from similar short channel effects as Planar MOSFET Nano wire FET still needs many improvements. A change in channel material is also possible but again fabrication and integrating them on silicon chips will be a difficult task. Different designs have also been experimented by companies for better performance. Further, we can use the following transistors: Tunnel Field Effect Transistor (TFET) 17 Carbon Nano tube Field-effect Transistor (CNFET) 24 REFERENCES Dick James, “High-k/Metal Gates in Leading Edge Silicon Devices” ASMC 2012 Natarajan, et al.
“A 14nm Logic Technology Featuring 2nd-Generation FinFET , Air-Gapped Interconnects, Self-Aligned Double Patterning and a 0.0588 ?m2 SRAM cell size”, IEDM 2014 Narasimha, S., et al., “22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL”, IEDM 2012. S-Y Wu et al., “A 16nm FinFET CMOS Technology for Mobile SoC and Computing Applications”, IEDM 2013 J. Fan, M. Li, X. Xu, Y.
Yang, H. Xuan, and R. Huang, “Insight into gate-induced drain leakage in silicon nanowire transistors,” IEEE Trans. Electron Devices, vol. 62, no.
1, pp. 213–219, Jan. 2015. J. Hur et al., “Comprehensive analysis of gate-induced drain leakage in vertically stacked nanowire FETs: Inversion-mode versus junctionless mode,” IEEE Electron Device Lett., vol. 37, no.
5, pp. 541–544, May 2016. S. Sahay and M.
J. Kumar, “Controlling L-BTBT and volume depletion in nanowire JLFETs using core–shell architecture,” IEEE Trans. Electron Devices, vol. 63, no. 9, pp. 3790–3794, Sep.
2016. S. Sahay and M. J. Kumar, “Insight into lateral band-to-band-tunneling in nanowire junctionless FETs,” IEEE Trans.
Electron Devices, vol. 63, no. 10, pp E. Abbe´, “Beitrage zur theorie des mikroskops und der mikroskopischen wahrnehmung,” Arch. Mikrosc. Anat.
Entwicklungsmech. 9, 413 – 468 (1873). R. Menon, H.
I. Smith, “Absorbance modulation optical lithography,” JOSA A. 23, 2290 (2006). T. L.
Andrew, H. Tsai, R. Menon, “Confining light to deep subwavelength dimensions to enable optical nanopatterning,” Science. 324, 917-920 (2009).
G. Pariani, R. Castagna, R. Menon, C. Bertarelli and A. Bianco, “Modeling absorbance-modulation optical lithography in photochromic films,” Optics Letters.
38, 16, 3024-3027 (2013). J.P. Colinge , A. Kranti, R. Yan, C.W. Lee, I.
Ferain, R. Yu, N. Dehdashti Akhavan, P. Razavi, ” Junctionless Nanowire Transistor (JNT): Properties and design guidelines” in Elsevier, Solid-State Electronics 65–66,pp.no 33-37, 2011. Elena Gnani, Antonio Gnudi, Susanna Reggiani, Giorgio Baccarani,”Theory of the Junctionless Nanowire FET ” IEEE Transactions on Electron Devices,Vol.58, pp.no 2903-2910, 2011.
Suman Datta , Huichu Liu, Vijaykrishnan Narayanan, “Tunnel FET technology: A reliability perspective” in Elsevier, Microelectronics Reliability 54 , pp.no. 861–874, 2014. Seongjae cho ,Hyungjin Kim, Heesauk Jhon, In man kang, Byung-Gook Park, James.S.Harris, ” Mixed mode simulation of nanowire Ge/GaAs Heterojunction TFET for circuit applications”, IEEE Journal of electron devices society,Vol.1,No.2, pp.no.48-53, 2013. Material Gate Nanoscale Tunnel Field-Effect Transistor”, IEEE transactions on Electron Devices,Vol.58,No.2, pp.no 404-410,2011 Arvind Soundarapandian, Ramanathan Gandhi, Zhixian Chen, Xiang Li, Navab Singh Sungjoo Lee , “Vertical Nanowire Gate-All-Around p-type Tunneling Field-Effect Transistor With Si0.8Ge0.2/Si Heterojunction,” in International Conference on Solid-State and Integrated Circuit , vol. 32, 2012 Field Effect Transistor, ” IEEE Electron device letters”, vol .34, pp.584-586, 2013 Frank, D.J., R.H. Dennard, E.
Nowak, P.M. Solomon, Y. Taur and H.S.P. Wong, 2001. Device scaling limits of Si MOSFETs and their application dependencies. Proc. IEEE, 89: 259-288 Gili, E., T.
Uchino, M.M.A. Hakim, C.H.D. Groot, P. Ashburn and S.
Hall, 2005. A new approach to the fabrication of CMOS compatible vertical MOSFETs incorporating a dielectric pocket. Proceedings of the 6th International Conference on ULtimate Integration of Silicon (ULIS), April 7-8, Bologna, Italy, pp: 127-130 WooJin Kim, et al. “Enjoy the Ultimate WQXGA Solution with Exynos 5 Dual”, EETimes, Jul 2012. Zhenjiang, Jiangsu, School of Electrical and Information Engineering, Jiangsu University,China, 17 July 2011. Javey, A., J.
Guo, D.B. Farmer, Q. Wang and D. Wang, 2004. Carbon nanotube field-effect transistors with integrated ohmic contacts and high-gate dielectrics. Nano.
Lett., 4: 447-450 Appendix A Tunnel Field-Effect Transistor (TFET) Device performance can be improved by scaling down of MOSFETs. Sub threshold leakage (OFF state) current is the major short channel effect in Nano scale MOSFET devices and is also highly temperature dependent. It increases with device scaling due to non-scalability of sub threshold slope and sequential decrease in the supply voltage (Vdd), for which the threshold voltage (Vth) has to be decreased to maintain essential device performance. To overcome this issue, alternative transistor designs are needed for energy efficient devices. One such device is the Tunneling Field-Effect Transistor (TFET).
Unlike MOSFET, which has thermionic injection-carrier diffusion as its transport mechanism, TFET uses tunneling as the carrier injection mechanism. Hence, it is possible for TFETs to achieve low OFF state current at room temperature. However, the ON state current of a Si TFET is several magnitudes lower than that of conventional Si MOSFETs due to the fact that Si has relatively larger band gap and effective tunneling mass. Therefore, devices with weak temperature dependence, novel geometry and different source material are necessary to enhance the device drive current. One such device is to hetero-Junctionless structure using various materials enhance the tunneling current. It is coupled with gate-all-around GAA nanowire structure gives excellent results due to proper electrostatic control of channel by the gate compared to planar devices.
Structure: The innermost structure is referred to as the Junction less cylindrical core and the gate is all around the cylindrical core depending upon the gate coverage region. Tox and Tsi are the thicknesses of the oxide region and the Junction less cylindrical core respectively. The total channel length is 20 nm and the gate material work function is of the 4.5 – 5.93 eV. Since it is of Junctionless type, the doping concentrations for source, drain and channel are similar and is of the range (Junctionless core) 1019 to 1021. Fig.
13 Schematic for Tunnel Field Transistor Appendix B Carbon Nanotube Field-Effect Transistor SINGLE-WALL carbon nanotubes (CNs) are considered to be one of the most promising candidates for post-CMOS applications, mainly owing to their smallness and ballistic trans-port properties. The ultrathin body of CNs (of the order of a few nanometers) allows for aggressive channel length scaling while maintaining excellent gate control. In general, a gate-all-around (GAA) structure is expected to be the ideal geometry that maximizes electrostatic gate control in FETs. Combining the ultrathin body of a CN with an GAA device geometry is a natural choice for ultimate device design. Dai et al have shown a CNFET with an “?” shaped dielectric coating exhibiting improved electrostatics.
However, a real GAA layout requires both the dielectric and the gate metal to completely wrap around the semiconducting channel. THE surface of CNs is known to be chemically inert to most reactions. Thin (<3 nm) uniform coating of a CN with a dielectric can only be achieved after modifying the CN surface by introducing some type of functional layer such as deoxyribonucleic acid (DNA). In order to obtain a GAA structure, the CN needs to be freestanding prior to the dielectric and gate metal deposition.
Without the assistance from the substrate, dielectric deposition becomes even more challenging. Fabrication: After functionalizing the nanotube with NO2, an ALD process is used to deposit a uniform Al2O3 film of 7 nm around the tube. A WN gate of 20 nm, also deposited by the ALD, is then wrapped around the dielectric. The wrapped CNs are then dispersed into solution and drop cast onto the desired substrate. Fig. 14 Schematic for CNFE Transistor
